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MC74HC157A Quad 2-Input Data Selectors / Multiplexers
High-Performance Silicon-Gate CMOS
The MC74HC157A is identical in pinout to the LS157. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device routes 2 nibbles (A or B) to a single port (Y) as determined by the Select input. The data is presented at the outputs in noninverted form. A high level on the Output Enable input sets all four Y outputs to a low level.
Features http://onsemi.com MARKING DIAGRAMS
16 16 1 PDIP-16 N SUFFIX CASE 648 1 16 16 1 SOIC-16 D SUFFIX CASE 751B 1 16 16 1 TSSOP-16 DT SUFFIX CASE 948F 1 16 16 1 SOEIAJ-16 F SUFFIX CASE 966 1 74HC157A ALYWG HC 157A ALYWG G HC157AG AWLYWW MC74HC157AN AWLYYWWG
* * * * * * * *
Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 82 FETs or 20.5 Equivalent Gates Pb-Free Packages are Available*
A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G = Pb-Free Package G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
June, 2005 - Rev. 9
Publication Order Number: MC74HC157A/D
MC74HC157A
A0 NIBBLE A INPUTS A1 A2 A3 B0 NIBBLE B INPUTS B1 B2 B3 SELECT OUTPUT ENABLE 2 5 11 14 3 6 10 13 1 15 PIN 16 = VCC PIN 8 = GND 4 7 9 12 Y0 Y1 Y2 Y3 DATA OUTPUTS
SELECT A0 B0 Y0 A1 B1 Y1 GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC OUTPUT ENABLE A3 B3 Y3 A2 B2 Y2
Figure 1. Pin Assignment
Figure 2. Logic Diagram FUNCTION TABLE
Inputs Output Enable H L L Select X L H Outputs Y0 - Y3 L A0 -A3 B0 -B3
X = don't care A0 - A3, B0 - B3 = the levels of the respective Data-Word Inputs.
ORDERING INFORMATION
Device MC74HC157AN MC74HC157ANG MC74HC157AD MC74HC157ADG MC74HC157ADR2 MC74HC157ADR2G MC74HC157ADTR2 MC74HC157ADTR2G MC74HC157AFEL MC74HC157AFELG Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) TSSOP-16* TSSOP-16* SOEIAJ-16 SOEIAJ-16 (Pb-Free) Shipping 500 Units / Rail 500 Units / Rail 48 Units / Rail 48 Units / Rail 2500 Units / Reel 2500 Units / Reel 2500 Units / Reel 2500 Units / Reel 2000 Units / Reel 2000 Units / Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74HC157A
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MAXIMUM RATINGS
SymbolIIIIIIIIIIIIII Parameter VCC Vin DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0III V V V - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 50 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature - 65 to + 150 260 _C _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package)
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter
Min 2.0 0
Max 6.0
Unit V V
DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND)
Vin, Vout TA
VCC
Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
- 55 0 0 0
+ 125 1000 500 400
_C ns
tr, tf
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit v 85_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9
Symbol VIH
Parameter
Test Conditions
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0
- 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9
v 125_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.2 3.7 5.2
Unit V
Minimum High-Level Input Voltage
Vout = VCC - 0.1 V |Iout| v 20 mA
VIL
Maximum Low-Level Input Voltage
Vout = 0.1 V |Iout| v 20 mA
V
VOH
Minimum High-Level Output Voltage
Vin = VIH |Iout| v 20 mA Vin = VIH
V
|Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA
2.48 3.98 5.48
2.34 3.84 5.34
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MC74HC157A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I II I I I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I II II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII II I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIII IIIIIIIIIIIIIIIIIIII II IIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIII I IIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I
Guaranteed Limit v 85_C 0.1 0.1 0.1 Symbol VOL Parameter Test Conditions VCC V 2.0 4.5 6.0 3.0 4.5 6.0 6.0 6.0 - 55 to 25_C 0.1 0.1 0.1 v 125_C 0.1 0.1 0.1 0.4 0.4 0.4 Unit V Maximum Low-Level Output Voltage Vin = VIL |Iout| v 20 mA Vin = VIL |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA 0.26 0.26 0.26 0.33 0.33 0.33 Iin Maximum Input Leakage Current Maximum Three-State Leakage Current Maximum Quiescent Supply Current (per Package) Vin = VCC or GND 0.1 0.5 1.0 5.0 1.0 10 mA mA IOZ Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND ICC Vin = VCC or GND Iout = 0 mA 6.0 4.0 40 160 mA NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
III I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I II IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III IIIIIIIIIIIIIIIII I II I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I II I I II I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I III I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII II
Guaranteed Limit v 85_C 130 85 26 22 140 90 28 24 125 80 25 21 95 32 19 16 10 Symbol tPLH, tPHL Parameter VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - - 55 to 25_C 105 65 21 18 110 70 22 19 v 125_C 160 115 32 27 165 115 33 28 150 110 30 26 110 36 22 19 10 Unit ns Maximum Propagation Delay, Input A or B to Output Y (Figures 1 and 4) tPLH, tPHL Maximum Propagation Delay, Select to Output Y (Figures 2 and 4) ns tPLH, tPHL Maximum Propagation Delay, Output Enable to Output Y (Figures 3 and 4) 100 60 20 17 75 27 15 13 10 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 4) ns Cin Maximum Input Capacitance pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 33
2f + I CC
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
CPD
Power Dissipation Capacitance (Per Package)*
pF
* Used to determine the no-load dynamic power consumption: PD = CPD VCC ON Semiconductor High-Speed CMOS Data Book (DL129/D).
VCC . For load considerations, see Chapter 2 of the
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MC74HC157A
PIN DESCRIPTIONS
INPUTS A0, A1, A2, A3 (Pins 2, 5, 11, 14)
Nibble A inputs. The data present on these pins is transferred to the outputs when the Select input is at a low level and the Output Enable input is at a low level. The data is presented to the outputs in noninverted form.
B0, B1, B2, B3 (Pins 3, 6, 10, 13)
The data present on these pins is in its noninverted form. For the Output Enable input at a high level, the outputs are at a low level.
CONTROL INPUTS Select (Pin 1)
Nibble B inputs. The data present on these pins is transferred to the outputs when the Select input is at a high level and the Output Enable input is at a low level. The data is presented to the outputs in noninverted form.
OUTPUTS Y0, Y1, Y2, Y3 (Pins 4, 7, 9, 12)
Nibble select. This input determines the data word to be transferred to the outputs. A low level on this input selects the A inputs and a high level selects the B inputs.
Output Enable (Pin 15)
Output Enable input. A low level on this input allows the selected input data to be presented at the outputs. A high level on this input sets all outputs to a low level.
Data outputs. The selected input Nibble is presented at these outputs when the Output Enable input is at a low level. SWITCHING WAVEFORMS
tr INPUT A OR B tPLH OUTPUT Y tTLH 90% 50% 10% tTHL 90% 50% 10% tf VCC tPHL GND tr SELECT tPLH OUTPUT Y tTLH 90% 50% 10% tTHL 90% 50% 10% tf VCC tPHL GND
Figure 3. HC157A
tr OUTPUT ENABLE tPHL OUTPUT Y tTHL 90% 50% 10% 90% 50% 10%
Figure 4. Y versus Selected, Noninverted
tf
VCC GND tPLH
tTLH
Figure 5. HC157A
TEST POINT OUTPUT DEVICE UNDER TEST C L*
*Includes all probe and jig capacitance
Figure 6. Test Circuit
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MC74HC157A
EXPANDED LOGIC DIAGRAM
A0 B0 A1 B1 A2 B2 A3 B3 OUTPUT ENABLE SELECT
2 3 5 6 11 10 14 13 15 1 12 Y3 9 Y2 7 Y1 DATA OUTPUTS 4 Y0
NIBBLE OUTPUTS
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MC74HC157A
PACKAGE DIMENSIONS
PDIP-16 N SUFFIX CASE 648-08 ISSUE T
-A-
16 9
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC74HC157A
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE A
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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CCC EEE CCC EEE CCC
K1
SECTION N-N
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MC74HC157A
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX CASE 966-01 ISSUE O
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74HC157A
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MC74HC157A/D

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